1. Field of the Invention
The present invention generally relates to methods and systems for measuring a characteristic of a substrate or preparing a substrate for analysis. Certain embodiments relate to methods and systems for measuring a characteristic of a substrate or preparing a substrate for analysis that include removing a portion of a material on a substrate.
2. Description of the Related Art
The following descriptions and examples are not admitted to be prior art by virtue of their inclusion within this section.
Fabricating semiconductor devices such as logic and memory devices typically includes processing a substrate such as a semiconductor wafer using a number of semiconductor fabrication processes to form various features and multiple levels of the semiconductor devices. For example, lithography is a semiconductor fabrication process that involves transferring a pattern from a reticle to a resist arranged on a semiconductor wafer. Additional examples of semiconductor fabrication processes include, but are not limited to, chemical-mechanical polishing, etch, deposition, and ion implantation. Multiple semiconductor devices may be fabricated in an arrangement on a semiconductor wafer and then separated into individual semiconductor devices.
Throughout the fabrication process, parameters of features formed on the wafer are measured for process monitoring and control purposes. For example, three-dimensional metrology of the profile of features on a monitor wafer is often performed at various times during the process. In particular, the three-dimensional profile of photoresist features is often measured after a lithography step to determine if the features have parameters that are within the specifications (specs) set for them. If the parameters of the features are within spec, then the lithography step may be performed on product wafers. On the other hand, if the parameters of the features are not within spec, then one or more parameters of the lithography step may be altered. Another monitor wafer may then be exposed in the lithography process, and the measurements described above may be performed until the parameters of the features are within spec.
The term “monitor wafer” is generally defined as a wafer upon which a semiconductor product will not be formed. Instead, monitor wafers are only used to monitor the parameters of one process tool and, therefore, are generally only processed in that one tool. After use, monitor wafers may be recycled or scrapped depending on the process that they were run through. Monitor wafers are particularly used as process monitors when a metrology or inspection process will damage the wafer. In this manner, monitor wafers, instead of product wafers, will be destroyed thereby reducing the costs of metrology or inspection. However, using monitor wafers to monitor and control processes can be relatively expensive if the monitor wafers are so damaged by metrology or inspection that they cannot be reused. In addition, since there may be significant differences between monitor wafers and product wafers (e.g., usually fewer processes are performed on the monitor wafers than the product wafers which can produce significant differences in the wafers), using monitor wafers may not provide results that are as accurate as measurements performed on a product wafer.
As a result, there are advantages to performing metrology and inspection on product wafers. However, as mentioned above, many metrology and inspection processes damage wafers. For example, wafers on which photoresist features are formed are often cleaved (i.e., fractured) through the photoresist features such that cross-sectional profiles of the features on the cleaved samples can be viewed. Since the wafers are fractured, this destructive metrology technique results in scrapped wafers. Another metrology technique involves photoresist feature cross-sectioning uses ion beams. For 193 nm photoresist features and smaller lines, the photoresist features are exposed to a tungsten or platinum deposition to reduce ion beam induced damage. The deposited metal top layer generates stresses on 193 nm photoresist lines thereby resulting in photoresist compression and deformation. This damage is due, at least in part, to the incomplete conformal coating of the substrate during the deposition process, which produces voids between adjacent photoresist features. The resulting cross-section thus loses structural integrity, and sometimes to such a degree that the results are not a viable indicator of the characteristics (e.g., critical dimension) of the features. In addition, in such metrology techniques, the use of gallium or other metallic liquid ion sources produces metal contamination in the front end of the line (FEOL) portion of semiconductor device fabrication. There are, therefore, several disadvantages to the currently used three-dimensional metrology techniques including destroyed and therefore scrapped wafers, metal contamination, and/or deformed photoresist features.
As the dimensions of advanced semiconductor devices continue to shrink, the presence of defects in the semiconductor devices increasingly limits the successful fabrication, or yield, of the semiconductor devices. For example, a scratch formed on a wafer during chemical-mechanical polishing may cause an open circuit or a short circuit in, or complete failure of, one or more semiconductor devices formed in subsequent processing. Because fabrication of a semiconductor device includes many complex process steps, the adverse effects of defects on total yield may increase exponentially if a defect formed on a wafer in one manufacturing process step causes additional defects to be formed on the wafer in subsequent manufacturing process steps.
Accordingly, defect detection or “inspection” of semiconductor wafers is and will continue to be of significant importance in semiconductor development and manufacturing. In addition, the review and analysis of defects is of significant importance such that the cause of defects may be determined and hopefully corrected. The ability to remove device film layers (“de-layer”) at select locations in a controllable fashion is critical for defect review and analysis during the device fabrication process. For example, removing a device film layer may allow a better view of a defect, particularly a subsurface or partially subsurface defect. In addition, removing a device film layer may enable analysis of the defect composition to be performed with less interference from the surrounding film layer.
Current techniques for de-layering of a substrate utilize ion beam etching, laser ablative etching, or mechanical abrasion using a micro-tip. Focused ion beam etching utilizes gallium ions to stimulate etching. Laser ablative techniques utilize lasers to heat the surface of the substrate to cause chemical and thermal reactions that remove the films. The mechanical abrasion technique uses micro-tips to remove the films around the defect.
Of the current techniques, ion beam etching is the most mature technique used to de-layer devices. However, when using an ion beam to stimulate etching, gallium ions from a source are implanted into the films, which can lead to changes in the optical, electrical, and mechanical properties of the etched features and the surrounding areas. The presence of gallium ions on the device can limit further processing of the device and the wafer in the fab, which would result in scrapping the entire wafer. In addition, during focused ion beam etching, the etched material may be deposited in the surrounding areas on the wafer. The other techniques used for de-layering of a substrate also have several disadvantages. For example, the laser ablative technique has low etch selectivity. In addition, the mechanical abrasion method has limited applications to certain large defects and films.
Accordingly, it would be advantageous to develop methods and systems for three-dimensional metrology of features on a substrate and for de-layering a material on a substrate, which do not destroy, contaminate, or deform the substrate or the features.